SIPI Characterization Engineer
- Experience
- Senior
- Employment
- Full-time
- Company size
- Startup
Open to US only. Set where you work from to check your eligibility.
No BS summary
We are looking for a skilled and hands-on Signal Integrity, Power Integrity, and Characterization (SIPI) Engineer to join our hardware team. In this role, you will own electrical characterization of high-speed SerDes interfaces and power delivery networks across our AI accelerator compute systems. You will build and scale test automation infrastructure capable of covering thousands of channels, while collaborating closely with SIPI engineers and board designers to influence and validate designs from early concept through production.
Core skills
Required skills
Optional skills
Required languages
What MatX Is Building MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. About the Role We are looking for a skilled and hands-on Signal Integrity, Power Integrity, and Characterization (SIPI) Engineer to join our hardware team. In this role, you will own electrical characterization of high-speed SerDes interfaces and power delivery networks across our AI accelerator compute systems. You will build and scale test automation infrastructure capable of covering thousands of channels, while collaborating closely with SIPI engineers and board designers to influence and validate designs from early concept through production. What You'll Do SerDes Characterization & Validation
Characterize high-speed SerDes interfaces (PCIe, Ethernet, custom protocols) including BER testing, eye diagram analysis, and PVT characterization Tune and optimize SerDes Tx and Rx equalization settings Perform channel characterization including insertion loss, return loss, and crosstalk measurements using VNA and time-domain reflectometry (TDR) Develop and execute correlation methodologies to align simulation predictions with measured results; drive feedback loops to improve modeling accuracy
Power Integrity Characterization
Measure and analyze high-current power rail transient noise and dynamic voltage droop on complex accelerator power delivery networks Characterize PDN impedance from board through package and silicon, and compare against target impedance specifications Identify PDN design weaknesses and collaborate with power delivery and board design teams to define and validate mitigation strategies
Test Automation & EDVT
Architect, develop, and maintain scalable test automation frameworks for Electrical Design Validation Testing (EDVT) across thousands of SerDes channels on multi-chip accelerator compute systems Integrate lab instruments (oscilloscopes, BERTs, VNAs, power analyzers) into automated test flows using Python or equivalent scripting environments Build robust data pipelines for test result collection, statistical analysis, and visualization to enable rapid triage and design decisions
Design Collaboration
Partner with SIPI engineers on optimization for advanced package designs, including die-to-die interconnects, bump arrays, and interposer structures Collaborate with board designers on PCB stackup definition, trace routing rules, via optimization, and decoupling strategies for high-speed accelerator boards Provide characterization data and actionable recommendations to influence layout guidelines, design rules, and future silicon/package revisions
What We're Looking For Experience & Education
5–10 years of industry experience in hardware characterization, SI/PI engineering Bachelor's degree or higher in Electrical Engineering; advanced degree a plus Deep understanding of high-speed SerDes architecture and operation — PHY layer fundamentals, equalization, jitter decomposition, and link margin analysis Strong grasp of transmission line theory — wave propagation, impedance matching, reflections, skin effect, and dielectric loss Solid understanding of PDN design principles — target impedance, resonance, bypass capacitor placement, and voltage regulator loop dynamics Hands-on proficiency with lab equipment Experience writing test automation scripts in Python (preferred)
Bonus Points
Background in AI accelerator or GPU system validation Familiarity with JEDEC or PCIe compliance testing methodologies Experience with statistical process control (SPC) or large-scale data analysis for silicon characterization Ability to do layout review for PCB, and advanced package design is a plus
Compensation The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.
Early Career - $120,000 - $250,000 + equity Mid Career - $175,000 - $362,500 + equity Senior Career - $250,000 - $475,000 + equity
What We Offer
A Stake in our success A flexible cash equity compensation mix that fits your needs Heath & Wellness Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t) Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year Support to Parents Up to 12 weeks of paid parental leave, regardless of your path to parenthood Learning & Development $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities Team Connection Team Lunches, quarterly off-sites, and regular town halls Financial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don’t! Fl
What you'll do
- Characterize high-speed SerDes interfaces (PCIe, Ethernet, custom protocols) including BER testing, eye diagram analysis, and PVT characterization
- Tune and optimize SerDes Tx and Rx equalization settings
- Perform channel characterization including insertion loss, return loss, and crosstalk measurements using VNA and time-domain reflectometry (TDR)
- Develop and execute correlation methodologies to align simulation predictions with measured results; drive feedback loops to improve modeling accuracy
- Measure and analyze high-current power rail transient noise and dynamic voltage droop on complex accelerator power delivery networks
- Characterize PDN impedance from board through package and silicon, and compare against target impedance specifications
- Identify PDN design weaknesses and collaborate with power delivery and board design teams to define and validate mitigation strategies
- Architect, develop, and maintain scalable test automation frameworks for Electrical Design Validation Testing (EDVT) across thousands of SerDes channels on multi-chip accelerator compute systems
- Integrate lab instruments (oscilloscopes, BERTs, VNAs, power analyzers) into automated test flows using Python or equivalent scripting environments
- Build robust data pipelines for test result collection, statistical analysis, and visualization to enable rapid triage and design decisions
- Partner with SIPI engineers on optimization for advanced package designs, including die-to-die interconnects, bump arrays, and interposer structures
- Collaborate with board designers on PCB stackup definition, trace routing rules, via optimization, and decoupling strategies for high-speed accelerator boards
- Provide characterization data and actionable recommendations to influence layout guidelines, design rules, and future silicon/package revisions
What they require
- 5–10 years of industry experience in hardware characterization, SI/PI engineering
- Bachelor's degree or higher in Electrical Engineering; advanced degree a plus
- Deep understanding of high-speed SerDes architecture and operation — PHY layer fundamentals, equalization, jitter decomposition, and link margin analysis
- Strong grasp of transmission line theory — wave propagation, impedance matching, reflections, skin effect, and dielectric loss
- Solid understanding of PDN design principles — target impedance, resonance, bypass capacitor placement, and voltage regulator loop dynamics
- Hands-on proficiency with lab equipment
- Experience writing test automation scripts in Python (preferred)
- Background in AI accelerator or GPU system validation
- Familiarity with JEDEC or PCIe compliance testing methodologies
- Experience with statistical process control (SPC) or large-scale data analysis for silicon characterization
- Ability to do layout review for PCB, and advanced package design is a plus
Benefits
- A Stake in our success A flexible cash equity compensation mix that fits your needs
- Heath & Wellness Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t)
- Time To Recharge 4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year
- Support to Parents Up to 12 weeks of paid parental leave, regardless of your path to parenthood
- Learning & Development $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities
- Team Connection Team Lunches, quarterly off-sites, and regular town halls
- Financial Wellbeing 401K and/or Roth IRA, with 5% company contribution, even if you don’t!
MatX is building custom silicon for large-language-model inference and training, with HW/SW co-design across ISA, RTL, simulator, compiler, and kernels so each layer benefits from the others. The runtime owns the host-side stack and the contracts that bind those teams together.