FuriosaAI
Signal/Power Integrity Engineer (On-/Off-Chip)
RemoteSouth Korea only
- Experience
- Lead
- Employment
- Full-time
Salary not disclosed
Check eligibility
Open to KR only. Set where you work from to check your eligibility.
No BS summary
Lead-level SI/PI engineer with 8+ years in component- and system-level signal/power integrity analysis. Must be South Korea-based and strong with lab instruments plus EDA tools such as SIwave, HFSS, ADS, HSPICE, Allegro, RedHawk-SC, SC-ET, or RedHawk-3DIC.
Core skills
SI/PI analysisSI/PI simulations
Required skills
VNATDRreal-time oscilloscopesSIwave/HFSS/ADS/HSPICE/Allegro/RedHwak-SC/SC-ET/RedHawk-3DIC
Optional skills
PCIeDDREthernetEM simulation tools
Responsibilities
- Define SI/PI requirements based on IP and system-level specifications.
- Perform SI/PI simulations at electromagnetic (EM), circuit, and system levels.
- Develop SI/PI methodologies for advanced packaging technologies such as chiplet, 3D-IC, D2D (die-to-die), and C2C (chip-to-chip) interfaces.
- Cover SI/PI analysis and optimization at the full system level, including on-chip, package, and PCB domains.
- Provide design guidance on stack-up, interconnect routing, PDN architecture, decoupling strategy, and component selection.
- Collaborate with silicon, package, and board teams to ensure accurate measurement-simulation correlation and system-level robustness.
- Support debug and bring-up efforts in the lab when needed.
- Work with internal teams and partners to co-optimize SI/PI solutions.
Minimum Qualifications
- BS or MS in Electrical Engineering, Physics, or a related field.
- 8+ years of experience in component- and system-level SI/PI analysis.
- Solid understanding of SI/PI fundamentals and methodologies.
- Hands-on experience with lab instruments such as VNA, TDR, and real-time oscilloscopes.
- Proficient in EDA tools such as SIwave, HFSS, ADS, HSPICE, Allegro, RedHwak-SC, SC-ET, or RedHawk-3DIC.
Preferred Qualifications
- PhD in Electrical Engineering, Physics, or a related field with 5+ years of relevant industry experience.
- Candidates with one or more of the following experiences will be given strong consideration:
- SI/PI analysis and optimization for high-speed digital systems and standard interfaces (e.g., PCIe, DDR, Ethernet)
- Model and analyze complex 3D structures using EM simulation tools
- On-chip Backend sign-off (Static/Dynamic IR, EM)
- On-/Off-chip PDN modeling and budgeting
- On-chip glitch/jitter/DVD analysis and sign-off methodology, including cross-talk, TSV uncertainty, and multi-corner/process derating
- Early-stage reference clock jitter estimation and sign-off methodology development
- Experience with on-chip clock sign-off, including clock design guide, 3DIC jitter derating, and multi-corner/process variation analysis.
Contact
- recruit@furiosa.ai
What you'll do
- Define SI/PI requirements based on IP and system-level specifications.
- Perform SI/PI simulations at electromagnetic (EM), circuit, and system levels.
- Develop SI/PI methodologies for advanced packaging technologies such as chiplet, 3D-IC, D2D (die-to-die), and C2C (chip-to-chip) interfaces.
- Cover SI/PI analysis and optimization at the full system level, including on-chip, package, and PCB domains.
- Provide design guidance on stack-up, interconnect routing, PDN architecture, decoupling strategy, and component selection.
- Collaborate with silicon, package, and board teams to ensure accurate measurement-simulation correlation and system-level robustness.
- Support debug and bring-up efforts in the lab when needed.
- Work with internal teams and partners to co-optimize SI/PI solutions.
What they require
- BS or MS in Electrical Engineering, Physics, or a related field.
- 8+ years of experience in component- and system-level SI/PI analysis.
- Solid understanding of SI/PI fundamentals and methodologies.
- Hands-on experience with lab instruments such as VNA, TDR, and real-time oscilloscopes.
- Proficient in EDA tools such as SIwave, HFSS, ADS, HSPICE, Allegro, RedHwak-SC, SC-ET, or RedHawk-3DIC.
- Preferred: PhD in Electrical Engineering, Physics, or a related field with 5+ years of relevant industry experience.
- Preferred: SI/PI analysis and optimization for high-speed digital systems and standard interfaces.
- Preferred: Model and analyze complex 3D structures using EM simulation tools.
- Preferred: On-chip Backend sign-off (Static/Dynamic IR, EM).
- Preferred: On-/Off-chip PDN modeling and budgeting.
- Preferred: On-chip glitch/jitter/DVD analysis and sign-off methodology, including cross-talk, TSV uncertainty, and multi-corner/process derating.
- Preferred: Early-stage reference clock jitter estimation and sign-off methodology development.
- Preferred: Experience with on-chip clock sign-off, including clock design guide, 3DIC jitter derating, and multi-corner/process variation analysis.
FuriosaAI works on NPU-based inference and serving systems for AI datacenters.
AI Hardwarefuriosa.ai/
Details
Apply routeDom
Salary not disclosed